JTAG-SMT2: Surface-mount Programming Module

The joint test action group (JTAG)-SMT2 is a compact, complete and fully self-contained surface-mount programming module for Xilinx^®field-programmable gate arrays (FPGAs). The module can be accessed directly from all Xilinx tools, including iMPACT™, ChipScope™, and EDK. Users can load the module directly onto a target board and reflow it like any other component. 

The JTAG-SMT2 uses a 3.3V main power supply and a separate Vref supply to drive the JTAG signals. All JTAG signals use high speed, 24mA, three-state buffers that allow signal voltages from 1.8V to 5V and bus speeds of up to 30MBit/sec. The JTAG bus can be shared with other devices as systems hold JTAG signals at high-impedance, except when actively driven during programming. The SMT2 module is CE certified and fully compliant with EU RoHS and REACH directives. The module uses a standard Type-A to Micro-USB cable available for purchase from Digilent, Inc. 

Users can connect JTAG signals directly to the corresponding FPGA signals. For best results, mount the module adjacent to the edge of the host PCB over a ground plane. Although users may run signal traces on top of the host PCB beneath the SMT2, Digilent recommends keeping the area immediately beneath the SMT2 clear. Note: Keep the impedance between the SMT2 and FPGA below 100 Ohms to operate the JTAG at maximum speed. The SMT2 improves upon the SMT1 with the addition of three general purpose IO pins (GPIO0 – GPIO2) and support for interfacing IEEE 1149.7-2009 JTAG targets in both 2 and 4-wire modes.

Note:

This module is not needed for Digilent FPGA boards as our boards are designed with this functionality natively.

Stats:

Processor/IC: Analog Devices^® ADP123AUJZ Linear Regulator

Connector(s): USB2 micro-AB

Programming: Works with all Xilinx tools. Fully supported by Digilent's Adept software and Adept SDK

Features:

• Small, complete, all-in-one JTAG programming/debugging solution for Xilinx FPGAs
• Compatible with all Xilinx tools
• Compatible with IEEE 1149.7-2009 Class T0 – Class T4 (includes 2-Wire JTAG)
• GPIO pin allows debugging software to reset the processor core of Xilinx’s Zynq™ platform
• Single 3.3V supply
• Separate Vref drives JTAG signal voltages; Vref can be any voltage between 1.8V and 5V.
• High-Speed USB2 port that can drive JTAG/SPI bus at up to 30Mbit/sec (frequency settable by user)
• SPI programming solution (modes 0 and 2 up to 30Mbit/sec, modes 1 and 3 up to 2Mbit/sec)
• Uses micro-AB USB2 connector
• Small form-factor surface-mount module can be directly loaded on target boards
• A similar circuit is available as a stand-alone programming cable; see Digilent’s JTAG-HS2.
• Analog Devices ADP123AUJZ Linear Regulator
• Fully supported by Digilent's Adept software and Adept SDK.

Support Materials:

Datasheet (PDF)

Schematics (PDF)

For all other material:

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